บทเรียนเซมิคอนดักเตอร์
ครบทุกสาย

Band theory, carrier transport, p-n junction, quantum mechanics พื้นฐาน

การทำงานของ MOSFET, I-V characteristics, threshold voltage, short-channel effects

CMOS logic gates, static/dynamic logic, propagation delay, noise margin

ภาพรวมกระบวนการผลิต IC ตั้งแต่ silicon substrate จนถึง finished chip

SRAM, DRAM, Flash (NAND/NOR) — cell structure, read/write operation

RTL → Synthesis → P&R → Tapeout — ภาพรวม full VLSI design flow

SPICE netlist, transient/DC/AC analysis, ngSPICE, HSPICE

Register-Transfer Level design, Verilog HDL, FSM, and pipelining structures

VHDL syntax, entity/architecture, concurrent/sequential statements

Metastability, synchronizers, async FIFOs, reset sync, and lint checking

Universal Verification Methodology, testbench, agent, scoreboard

Technology mapping, optimization, DC Compiler, QoR metrics

Synopsys Design Constraints (SDC), timing paths, PrimeTime setup/hold timing closure

Die floorplan, power domain, macro placement, power planning

Placement, routing, Innovus/ICC2, congestion, DRC fixes

Design rule check, layout vs schematic, Calibre, Mentor

GDS generation, full-chip signoff checklist, foundry submission

Power gating, clock gating, DVFS, multi-Vt, UPF flow

FinFET vs planar MOSFET, fin formation, 3D gate structure

Czochralski crystal growth, wafer slicing, polishing, epitaxial layer

ISO Class 1-10, particle contamination control, HEPA/ULPA filters

Optical photolithography process, photoresist chemistry, and resolution enhancement

ASML NXE platform, LPP source, 13.5nm wavelength, throughput

Optical proximity correction, SRAF, inverse lithography, mask data prep

SiO₂ growth (dry/wet), Deal-Grove model, gate oxide quality

CVD, PVD, ALD overview; wet/dry etch, selectivity, anisotropy

Self-limiting reactions, high-k dielectrics (HfO₂), conformal films

Dopant implantation (B, P, As), Bragg peak, channeling, annealing

Wet chemical etching and dry plasma etching (RIE/DRIE), selectivity, and aspect ratio

Chemical mechanical planarization, slurry, dishing, erosion, endpoint

Single/dual damascene, Cu electroplating, barrier layer, RC delay

Back-end-of-line metal layers, via formation, contact resistance

Inline measurement tools including CD-SEM, TEM, AFM, and XRD material characterization

Yield models, defect density, Poisson/Seeds, DOE methodology

กระบวนการตรวจจับ defect ด้วยแสง/e-beam, การวิเคราะห์ Pareto และระบบควบคุมคุณภาพด้วยสถิติ (SPC)

Power devices landscape, on-resistance, breakdown voltage, Baliga FOM

SiC vs GaN vs Si properties, critical field, electron mobility, thermal conductivity

4H-SiC epitaxy, gate oxide reliability, channel mobility, switching loss

AlGaN/GaN heterostructures, 2DEG, GaAs pHEMT, normally-off design, power and RF applications

IGBT structure, latch-up, tail current, IGBT vs SiC MOSFET tradeoffs

Traction inverter, OBC, DC-DC converter, thermal management in EV

สถาปัตยกรรมตัวถังโมดูลกำลัง, แผ่นซับสเตรต DBC/AMB, การต่อลวด (Wire Bonding) และการทดสอบความน่าเชื่อถือ

Amplifier topologies, feedback, stability, small-signal model

Differential pair, gain-bandwidth, CMRR, two-stage op-amp design

Phase-locked loop, VCO topology, phase noise, loop bandwidth

Design methodologies for Low Noise Amplifiers (LNA), Mixers, and Power Amplifiers (PA)

Scattering parameters, Smith chart, port matching, stability circles

AlGaN/GaN heterostructures, 2DEG, GaAs pHEMT, normally-off design, power and RF applications

Parametric, functional, IDDQ testing, test coverage, test economics

Automated Test Equipment architecture, instrumentation, and program testing on V93000 & UltraFLEX

Scan chains, ATPG pattern generation, MBIST, and JTAG boundary scan architectures

Probe card, wafer map, bin distribution, sort flow, yield analysis

OSAT ecosystem, wire bond, flip chip, BGA, WLCSP packaging types

AEC-Q100/101 automotive compliance, HTOL, and burn-in reliability qualification flow

GAA Nanosheet FET, TSMC N3E process, N2 node architecture

RibbonFET GAA, PowerVia backside power delivery, 20A/18A process

เจาะลึกเทคโนโลยี GAA/MBCFET ระดับ 2nm ของ Samsung Foundry แผนงาน SF2P/SF2Z และความท้าทายด้าน Yield

NA=0.55, anamorphic optics, 2nm node patterning capability

Backside PDN, buried power rail, IR drop reduction, TSMC/Intel/Samsung

Chip-on-Wafer-on-Substrate, InFO fan-out, HBM integration for AI chips

3D stacking with Cu-Cu hybrid bonding, wafer-on-wafer, die-on-wafer

Complementary FET, vertically stacked nFET/pFET, sub-2nm roadmap

Monolayer channel materials, TMD transistors, CVD growth, IRDS outlook

GPU vs NPU vs TPU, systolic arrays, memory bandwidth wall, chiplet AI