SemiMatrix
quantum dimension scaler

Leading Edge Nodes Explorer

ทดสอบระดับอุปกรณ์ฟิสิกส์กึ่งตัวนำ วิเคราะห์ความต่างของโครงสร้างทรานซิสเตอร์แบบ FinFET และ Gate-All-Around (GAA) Nanosheet จนถึง CFET ในสเกลต่ำกว่า 3nm

TRANSISTOR 3D DIAGRAM — ISOMETRIC VIEW
QUANTUM ENERGY BAND DIAGRAM — BAND BENDING & TUNNELING
Quantum Energy Band Diagram Ef (Fermi) Ec (Conduction) Ev (Valence) Oxide (Tox)
SEMICONDUCTOR QUANTUM TELEMETRY — LIVE
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Node Physical Specifications

TSMC

N3E (3nm)

ArchitectureFinFET (3-Gate)
Density~220M tr/mm²
Power Reduction25-30% vs N5
Perf Gain10-15% vs N5
EUV Layers20+ Layers
Samsung

SF2 (2nm)

ArchitectureGAA MBCFET
Density~310M tr/mm²
Power Reduction30% vs SF3
Perf Gain12% vs SF3
EUV Layers25+ Layers
Intel

18A (1.8nm)

ArchitectureGAA RibbonFET
Density~350M tr/mm²
Power Reduction35% vs Intel 4
Perf Gain15% vs Intel 4
Backside PowerPowerVia
Emerging

CFET (1.4nm)

ArchitectureComplementary FET
Density~550M tr/mm²
Power Reduction45% vs 18A
Perf Gain22% vs 18A
Stacking TypeVertical 3D (n/p)